Digital Design Engineer IP Level (M/F)

Location

Maisons Laffitte, Yvelines | France

Job description

About SiPearl…

Founded in 2019 by Philippe Notton and financed by the European Union, SiPearl embodies Europe's dream of mastering the technological heart of its supercomputers: the microprocessor.

SiPearl is building Rhea, the world's first energy-efficient #HPC-dedicated microprocessor designed to work with any third-party accelerator (#GPU, #AI, #quantum). It will help Europe solving major challenges in medical research , artificial intelligence, security ️, energy management and climate while reducing its environmental footprint.

Since our creation in 2019, we host 170 collaborators in 6 offices: France (Maisons-Laffitte, Massy, Grenoble, Sophia Antipolis), Germany (Duisburg), Spain (Barcelona).

After a successful series A in 2023 (90M €), SiPearl has recently won an emblematic contract to equip Europe’s first exascale supercomputer, JUPITER, who will be operated by the EuroHPC’s center of research from Jülich (Germany). And as the dream of a European machine, crossing the 1 billion billion mark calculations per second thanks to an European microprocessor, is becoming reality, SiPearl is willing to hire 150 engineers by the end of 2024!

What a regular day at the job might look like:

• Reading and analysing the system requirements and architecture requirement documents
• Participating in make-or-buy analysis
• Assisting in the definition of project milestones and deliverables
• Developing features in Verilog/SystemVerilog including simulation and implementation
• Writing design and user documentation
• Collaborating with other teams
• Participating to design methodology improvements

What would make you succeed in this role:

• VHDL/ Verilog/SystemVerilog developments
• Design of complex SoC
• Design of high performances IP blocks
• ARM/AMBA and standard interfaces
• Cosimulation by writing tests in embedded C.
• Scripting using languages like Bash/Perl/Python/Tcl
• Implementation trials on ASIC and/or FPGA (logic synthesis, Static Timing Analysis)
• Version management tools
• Continuous Integration and delivery tools 

➕ Experience in the following is a plus:

• Git
• Gitlab
• ARM ecosystem (Cores, Noc, …)
• DFT related activities
• UVM
• Simulation Coverage
• Power and related aspects of multi voltage design
• Synopsys tools (Spyglass, DC, Primetime)

Dear candidate, even if you consider you do not fulfill all the qualifications mentioned above, please still apply and share with us why you believe you would be a good fit.

Recruitment process

✔️Discovery interview with our Talent Acquisition Partner (30')

✔️ Personality test - no need to worry, there is no wrong or right answer; our goal is to get to see beyond your resume (45')

✔️ Technical interview (1h)

✔️ Interview with your future manager (1h) 

Benefits and conditions:

• Contract: CDI

• Benefits : meal vouchers (Sodexo), health insurance (70% covered by SiPearl), 8 to 9 RTTs, 5 days per year of remote work from any EU location
  

• Work model : On-Site/Hybrid (2 days remote)

• Location: Maisons-Laffitte ou Massy

• Awesome activities such as: Hackathons, Training Challenges, Quarterly Kick-off sessions, team events, Company events and much more

Are you curious to learn more about us?

• Follow us on LinkedIn to stay updated with our latest news
• Get updated about our recruiting activities: Sipearl careers webpage
• Get to know a bit more about our team culture: Welcome to the jungle

At SiPearl, we are dedicated to building a diverse and inclusive workplace that thrives on the strength of varied perspectives and backgrounds. We recruit talent based on merit, experience, and alignment with our company's goals and values.  
 

Job tags

Salary