SOC Engineering, Principal Engineer
Location
Portugal | Germany
Job description
Job Description and Requirements
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our System Solutions Group (SSG) delivers tool, methodology, design creation, verification and implementation expertise to enable leading edge customers to complete their most challenging SoC design projects. Our customers range from industry leaders to start-ups, developing products for applications such as telecommunications, wireless, broadband, automotive, AI, and high-performance computing. Our services work ranges from collaborating with customers to provide specific design skills and assistance for an SoC development, providing design flow and methodology deployment, performing RTL2GDSII implementation for blocks, sub-systems and full SoCs, and executing full SoC turnkey design from specification to parts.
We’re looking for a Senior SoC Engineer – Physical Design Specialist. Does this sound like a good role for you? In this role you will perform SoC Physical Design implementation (RTL2GDSII) at block and chip levels as well as provide RTL2GDSII design flow methodology expertise.
Key Qualifications: - BSEE/MSEE/PHD in Electrical and/or Computer Engineering.
- At least 5 years’ experience in delivering physical implementation on SoCs
- Experience with Synopsys RTL2GDSII toolset including Design Compiler, IC Compiler, Fusion Compiler, PrimeTime, StarRCXT and ICV.
- Experience with synthesis, place and route, clock implementation, SoC power implementation, SoC timing analysis, and physical verification
Preferred Additional Qualifications: - Experience with Block and SoC level constraints tuning and development
- Experience with Low Power designs (multi-supply, shutdown, DVFS, etc), developing low power UPF constraints and implementing UPF designs
- Experience with basic test structures and scan insertion and understanding/tuning DFT Constraints
- Experience with timing/power fixes and ECO flows
- Experience closing timing in high-speed designs and leading edge technologies
- Experience with physical implementation of Arm-based sub-systems
- Knowledge of SoC standard interfaces including (but not limited to) PCIe, DDR, HBM, SERDES, MIPI CSI/DSI, SPI, I2C, I3C, and other
- Understanding of process variation (OCV, POCV, AOCV, LVF, MLVF, etc)
- Experience working in a customer focused environment with great communication skills
- Will be able to travel on occasion for short periods of time, and occasionally work on-site at customer premises as required
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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