TekWissen LLC
Location
Markham, ON | Canada
Job description
Overview:
TekWissen Group is a workforce management provider throughout the USA and many other countries in the world. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.
Job Title: Physical Design Engineer
Work Location: Markham ON L3T 7X6
Duration: 15 Months
Work Type: Contract
Job Type: Onsite
Job Description:
THE ROLE:
Physical Designs Power Optimization is critical hot topic in IC Physical design.
In this position you will work with global physical design team for client AI accelerator/GPU/APU chips physical design power optimization/reduction.
Focus on physical design methodologies implementation to improve chip power consumption from Synthesize to place & route.
The individual is expected to be an expert in digital physical design it is a plus to have strong ability in FrontEnd or RTL coding experience or Synthesis.
The individual is expected to know backend physical design very well.
THE PERSON:
Strong selfmotivation for technical topics quick and deep learner strong communication skill within global engineering team strong team spirit help and support team members.
KEY RESPONSIBILITIES:
Implement stateofart physical design power optimization methodologies into SOC project
Maintain and enhance the power optimization methodologies in physical design flow
Closely collaborate with SOC project design team help/support/drive them to adopt the physical design power optimization methodology
PREFERRED EXPERIENCE:
Preferred 5 years or more years of experience in physical design in digital ASIC chips
Strong PnR STA IR/EM PV knowledge/experience
Be familiar with physical design power optimization methodologies (eg. Clockgating powergating activity aware PnR power friendly floorplan DVFS multibit rebanking debanking scan path power etc.)
Expertise in BackEnd (physical design) EDA tools especially the power calculation/optimization tools PTPX
Strong flow develop and custom script develop ability
Successfully gone through several complete product development cycles
Works well with crossfunctional teams
Good communication skills strong interpersonal skills and the flexibility
ACADEMIC CREDENTIALS:
Preferred MSEE with 3 years or Bachelor with 5 years of industrial experience in ASIC design
TekWissen Group is an equal opportunity employer supporting workforce diversity.
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