R&D Engineering, Staff Engineer
Location
Nepean, ON | Canada
Job description
Job Description and Requirements
ASIC Physical Design Methodology Engineer. We are looking for an
ASIC Physical Design Methodology Engineer to join the Digital Methodology Core Team. In this position, you will design, develop, and manage infrastructures, processes, methodologies, and checklists for the complete portfolio of Mixed-Signal IP. This is a position with opportunities to learn, grow and establish yourself as the go-to person for Software EDA teams and Silicon IP teams. You will be the gatekeeper of quality for our ASIC (Application Specific Integrated Circuit) products going out the door and will interface with teams to help improve the methodologies, improve their experience and our customers’ experience. This is a highly visible role in which you will be given the chance to take on larger tasks as you grow.
The successful candidate will have technical experience in at least two aspects of ASIC development covering anything from Front-End Development (RTL and Verification) to Back-End Development (PNR). You are also expected to have strong systems level thinking and with the ability to write code in a variety of scripting languages: C++, Perl and Python.
You will be successful in this role if you are willing to build and grow status reporting skills, leadership skills and aspire for breadth of technical understanding. This role will require matrix interactions, and collaboration, Strong verbal and written communication skills will be valued highly.
Key job responsibilities - Create and support innovative Front-End and Physical Design Methodologies by leveraging feedback from our EDA and Silicon IP teams
- Support Silicon IP teams, by integrating Methodologies into their development infrastructures and showing successful results
- Support, and maintain our regression infrastructure to manage change, and revise methodologies on a regular basis
- Test a range Silicon IP through our Methodologies centered around Software EDA tools
Qualifications - Bachelor's/Master's degree in electrical or computer engineering and computer science
- 5+ years of experience running Front-End and Back-End Synthesis in advanced technology nodes, and using state-of-the-art EDA tools such as DC, ICC2, FC (Fusion Compiler)
- 3+ years of experience driving designs through EDA tools such as TetraMax, SpyGlass, VC SpyGlass, Z01X, TCM (Fishtail), PrimePower and VCS
- 2+ years' experience writing code in RTL for synthesis or System Verilog for Functional Verification
- Strong experience writing in TCL, Perl, and/or Python
- Familiarity with multi-clock designs, and understanding of Clock-Domain-Crossing principles
- Understanding of Machine Learning Concepts and AI
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].
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