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Location

Nepean, ON | Canada

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Job description

Job Description and Requirements

As a Staff A&MS Layout Engineer you will collaborate in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global DDR teams in developing layout for complex analog mixed-signal designs in the latest technology nodes. In your role you will be responsible for contributing to the overall development of layout flows, automation, and methodology within the layout organization. Including the creation and verifying common block layouts, test structures and assessing layout designs in new technologies.

Responsibilities and Duties

• Assist in creation, testing and documentation of new layout tools and flows
• Coordinating with other layout team members in designing and reviewing layout designs
• Collaborate with circuit team for feasibility layout of new products
• Assisting ongoing projects with specialty layout or in resolving issue
• Optimize layout designs for performance, power, and area
• Work with RnD Experts to perform layout verification and resolve any design-related customer issues
• Create common blocks or unit cells in new technology nodes for enablement

Qualifications

• 4+ years of direct industry experience in A&MS Layout design is required. 
• In depth knowledge with layout of analog and mixed signal CMOS circuits
  • Experience in development of DDR subcircuit layout (RX, TX, LCDL) a plus
• Proficient with full custom analog layout design tool: Custom Compiler (or equivalent)
• Prior knowledge and proficiency of schematic driven layout editor tools such as Custom Compiler SDL or Virtuoso XL or is required.
• Must have a solid working knowledge of DRC, LVS and be able to debug results from ICV/Calibre tools
• Experience with advanced FinFET nodes
• Should be familiar with using foundry design rule manuals to debug DRC errors
• Good written and verbal English skills
• Skilled with TCL, SKILL, PERL, Python or other language scripting.
• Experienced with MS Office tools like Word, Excel, PowerPoint, SharePoint, Visio, etc...
• Proficient with
  • Layout design with consideration for reliability (EMIR/DFM)
  • Layout design to optimize for parasitic layout effects (matching/proximity effects)
  • Layout optimization for signal integrity (clock/data routes, differential routing, shielding)
  • Implementation of ESD design constraints, latch-up risk mitigation
  • Skilled with PERC a plus
• Has excellent communication skills, ability to interact with cross-functional teams
• Other pluses are:
  • Experience in working with Jira/Atlassian (or other such) tools
  • ICV Work Bench or Calibre DRV
  • ICC/ICC2/Fusion Compiler a plus

#LI-DP1
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

 

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].

 

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Salary